To prevent the output of an erroneous analog output signal when supplying input data having an error to a digital/analog (D/A) converter having a serial interface.

A D/A converter 147 has the serial interface. In data D1-Dn as control signals from latch circuits 146-1 to 146-n, data presenting input data DATA, a strobe signal STROBE and a clock signal CK are supplied to the D/A converter 147. A mask circuit 148 is provided on the supply path of the strobe signal STROBE. When a D/A converter transmission error is detected by a parity detecting circuit 145 and there is the danger of error in any one of address data or gain control data comprising the data stream of one partition of the input data DATA, the strobe signal STROBE to the D/A converter 147 is masked by the mask circuit 148.