Title:
AC/DC CONVERTER FOR MULTIPLE REGULATION AC
Document Type and Number:
Japanese Patent JP2819255
Kind Code:
B2
Abstract:
PURPOSE: To detect missing of cycle by providing a timer being reset every time when a reference voltage intersects, measuring a predetermined lag behind each reset time and generating a control signal when the lag reaches a given value.
CONSTITUTION: When missing of cycle takes place, zero-cross of AC input does not take place during an interval and a third counter 35 is not reset but continues counting to the end of the interval. When the output becomes highb to reset a counter 37, a high output is generated from a gate 67 through gates 63, 65 and a clock pulse is transmitted thus generating the firing pulse for a triac. When a next effective zero-cross is detected, the counter is reset to generate pulses continuously until a fourth counter 37 counts for a fixed time. The fixed time is equal to at least one period of the lowest predicted frequency of an AC power supply and when missing of cycle is sustained longer than one cycle, generation of triac pulse subsequent to a control circuit is interrupted and missing of cycle can be detected.
Inventors:
Munimohan
Application Number:
JP1826695A
Publication Date:
October 30, 1998
Filing Date:
February 06, 1995
Export Citation:
Assignee:
SGS-Thomson Microelectronics Proprietary Limited
International Classes:
H02M7/06; H02M1/10; H02M7/10; (IPC1-7): H02M7/10; H02M7/06
Attorney, Agent or Firm:
Fumio Sasashima
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