To shorten a period in which an output terminal becomes high impedance and to reduce the influence of noise received from the outside by providing an adjustment circuit for adjusting the duty factor of clock signals.

In the case that this D/A converter is a D/A converter of 1 bit, in order to improve D/A conversion accuracy, after PWM signals are converted to PDM signals, the PDM signals are outputted to a low-pass filter and high frequency components are removed. In order to shorten the period in which the output terminal 15 becomes a high impedance state as much as possible and to reduce the influence of the noise from the outside, the duty factor of CLOCK is adjusted so as to make the period in which a counter is at H level shorter than the period in which it is at L level. In such a manner, by providing the counter 13 for adjusting the duty factor of the CLOCK for establishing the synchronization of the PWM signals at a falling edge, the period in which the output terminal 15 becomes the high impedance state is shortened and the influence of the noise from the outside is reduced.