Title:
D/A CONVERTER
Document Type and Number:
Japanese Patent JP2940759
Kind Code:
B2
Abstract:
PURPOSE: To reduce the distortion of the output of a PWM type D/A converter.
CONSTITUTION: Outputs A1-A3 of a counter 20 are inverted by an inverting circuit 23 in the former half period of a data conversion period T1, and an adding circuit 22 adds 1 in the latter half period. Outputs a1-a3 obtained by respective processes are inputted to XOR gates 24-26 together with digital data D1-D3 and the outputs of those XOR gates 24-26 are inputted to a NOR gate 27. The output of the NOR gate 27 is supplied to the set side of a flip-flop 33 by a switching circuit 30 in the former half period of the data conversion period T1 and supplied to the reset side in the latter half period. Consequently, a pulse with width corresponding to the contents of the digital data D1-D3 is set in every data conversion period T1 as the output C1 of the flip-flop 33. Then different potentials V1 and V2 are composed according to the output C1.
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Inventors:
MURATA TSUTOMU
YAMADA YASUHIRO
YAMADA YASUHIRO
Application Number:
JP11610893A
Publication Date:
August 25, 1999
Filing Date:
May 18, 1993
Export Citation:
Assignee:
SANYO DENKI KK
International Classes:
H03M1/82; (IPC1-7): H03M1/82
Domestic Patent References:
| JP4196621A | ||||
| JP2165729A | ||||
| JP61173523A | ||||
| JP6139729A | ||||
| JP60100830A | ||||
| JP5587037U |
Attorney, Agent or Firm:
Koji Yasutomi (1 person outside)