PURPOSE: To realize an A/D converter with simple constitution adjusting the switching clock of a switched capacitor filter impartially and uniformly.

CONSTITUTION: An analog signal is fed to a band pass switched capacitor filter 101, from which only a signal band component is outputted and it is converted into a digital signal by an A/D converter section 102. On the other hand, the value of a primary basic frequency division ratio setting section 106 is incremented/decremented by a ±1 adder section 105 in response to the value of a primary adjustment frequency division ratio setting section 107, and the result is outputted to a primary variable frequency divider section 103 as a frequency division ratio from a selector 104. Then the reference clock is frequency-divided by the frequency division ratio by the primary variable frequency divider section 103, frequency-divided by 1/2 at a 1/2 frequency divider section 108 and the result is outputted as a switching clock. On the other hand, the clock is frequency-divided at a secondary variable frequency divider section 109 by the value of a secondary frequency division ratio setting section 110 and the result is outputted to the A/D converter section 102 as a sampling operating clock.