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Title:
SERIAL/PARALLEL-PARALLEL/SERIAL CONVERTING CIRCUIT
Document Type and Number:
Japanese Patent JPS58170117
Kind Code:
A
Abstract:

PURPOSE: To vary the number of bits of words, by using a buffer register in which the data of a shift register is set in a receiving mode when a setting signal is produced and the own data is set to the shift register in a transmitting mode when the setting signal is produced.

CONSTITUTION: In a receiving mode, the serial input data are fetched successively into a shift register 1. The contents of the register 1 are shifted to buffer registers 2-0 and 2-1, and the contents of the registers 2-0 and 2-1 are read by a microprocessor 6. In a transmitting mode, the data are written into the registers 2-0 and 2-1 by the processor 6. Then the data of the registers 2-0 and 2-1 are set to the register 1, and the data of the register 1 are delivered successively by one bit.


Inventors:
ITOU YUUICHI
Application Number:
JP5160282A
Publication Date:
October 06, 1983
Filing Date:
March 30, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F13/00; H03M9/00; H04L13/10; (IPC1-7): G06F3/04; G06F5/04; H03K13/256; H04L13/14
Attorney, Agent or Firm:
Kyotani Shiro



 
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