PURPOSE: To attain stable voltage/frequency conversion with high accuracy by providing a frequency divider frequency-dividing a clock signal and an F outputting an output having a prescribed phase relation with the output of the frequency divider to synthesize properly the outputs of the frequency divider and the FF.
CONSTITUTION: A digital signal in response to an analog voltage to be converted from an A/D converter 5 is fed to a selector 6. On the other hand, a stable clock signal CL from an oscillator 1 is frequency-divided by a frequency divider 2 comprising pluralcounters connected in cascade an its output is given to the selector 6. Further, the FF3 gives an output inverted to the output of the frequency divider 2 and retarded by a half cycle of the clock CL and gives it to the selector 6. Then a selector 6 selects and synthesizes properly the outputs of the frequency divider 2 and the FF3 based on the output of the A/D converter 5. Thus, stable voltage/frequency conversion is attained with high accuracy.
JPS58206285A | 1983-12-01 | |||
JPS5496959A | 1979-07-31 |