Title:
A/D CONVERTING MODULE
Document Type and Number:
Japanese Patent JPH02118819
Kind Code:
A
Abstract:
PURPOSE: To take out the data without increasing a high order processing part load by holding converted data in a buffer memory for a constant time.
CONSTITUTION: An address counter 10 operates based on a control signal from a command control part 12 and supplies a synchronized address signal. A buffer memory 9 supplies cyclically the data supplied from a photocoupler 6 based on an address signal from the address counter 10 and a host computer and inputs the data through an address counter buffer 11 to a host computer. Further, the address counter 10 is cleared by an A/D starting instruction from the host computer, and the buffer memory 9 holds the data for a constant time.
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Inventors:
TERASAKI NOBUO
Application Number:
JP27280688A
Publication Date:
May 07, 1990
Filing Date:
October 28, 1988
Export Citation:
Assignee:
MEIDENSHA ELECTRIC MFG CO LTD
International Classes:
G06F3/05; (IPC1-7): G06F3/05
Attorney, Agent or Firm:
Fujiya Shiga (2 outside)