PURPOSE: To receive an instruction and an operand from a CPU one by one even in execution of an internal processing currently, and to contrive to improve the processing capability of the CPU, by storing the instruction and the operand in a stack memory of FIFO style capable of stacking them.

CONSTITUTION: The stack memory 2 stores a firmware start address 20, and an operand load number 21 at time of inputting the instruction, and an operand data on an external data line 11, at time of reading the operand, in a FIFO format, after adding data identification signals 23 on them, respectively. And the instruction and the operand for a coprocessor form the CPU are stored immediately in the stack memory 2, in the data format of an internal firmware start address B and an operand data. In this way, it is possible to execute the next instruction of the coprocessor, or other possible to execute the next instruction of the coprocessor, or other instructions by the CPU without a waiting time, thereby, the processing capability of the CPU can be improved.