Title:
CORRELATION FILTER AND CDMA RECEIVER
Document Type and Number:
Japanese Patent JP3269959
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide the correlation filter with a small power consumption that is used by a portable equipment.
SOLUTION: A delay circuit 1 provides an output of plural tap output signals TP1-TPn with different delay times and a weighting synthesis circuit 2 applies weighting/synthesis processing to the output signals to provide an output of a correlation output signal. The supply of power to the weighting synthesis circuit 2 is made while the correlation output signal is obtained from the weighting synthesis circuit 2 via a switch element 4 switched by a timing control circuit 3 producing a control signal based on the output signal from the weighting synthesis circuit 2, resulting that the application of power for substantially undesired processing periods is avoided to reduce the power consumption.
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Inventors:
Hiroko Ono
Masatoshi Takada
Kenzo Urabe
Masatoshi Takada
Kenzo Urabe
Application Number:
JP523596A
Publication Date:
April 02, 2002
Filing Date:
January 16, 1996
Export Citation:
Assignee:
Hitachi Kokusai Electric Co., Ltd.
International Classes:
H04B1/707; H03H21/00; H04B1/7093; H04J13/00; H04B1/16; (IPC1-7): H04B1/707
Domestic Patent References:
| JP8307428A | ||||
| JP6181424A | ||||
| JP795126A | ||||
| JP9116465A | ||||
| JP983486A | ||||
| JP6252887A |
Attorney, Agent or Firm:
Nobuhiro Funatsu (1 outside)