To provide a configuration of holding a count of a counter with a smaller circuit scale when the count of the counter reaches an expected value.

When the count of the counter 1 reaches the expected value (n) and a decoder 4 outputs a decode signal, a logic circuit comprising a NOT gate 11, a NAND gate 12 and a NOT gate 13 outputs an OR signal between the decode signal and a clock signal to a clock input terminal of the counter 1 to block the clock signal from being outputted to a D flip-flop 2 being a component of the counter 1.