To provide a counter circuit with a booby trap capable of operating at a high speed.

A counter circuit is provided with a plurality of flip flop circuits (FF circuits) #1-#5 successively connected for receiving a common clock signal and two input logical gates 11 and 12 whose one inputs are connected to the outputs of the corresponding FF circuits #1 and #2, and whose other inputs are connected to the common FF circuit #5, and whose output signals are applied to the next FF circuits #2 and #3. This booby trap is realized by the two input logical gates. A value to be inputted by each FF circuit is decided by the logical arithmetic operation of at most two logical values so that this can be applied to the high frequency of a clock signal CLK.