Title:
COUNTER CIRCUIT
Document Type and Number:
Japanese Patent JP3338722
Kind Code:
B2
Abstract:
PURPOSE: To simplify a software by applying '1' as the initial value of a counter so as to distinguish the reset of the counter from a system reset when the counter is reset by matching with a comparison register.
CONSTITUTION: Comparison registers 3 and 4 write/read held data between a data bus 201 through a transfer gate 2. Each time a clock signal 103 comes, an incrementer counts up the data held by a counter 7 one by one. The comparison registers 3 and 4 compare those held data with the data held by the counter 7 and when both of them are matched, prescribed match signals 104 and 105 are outputted. Based on the match signals 104, an initialize control circuit 8 resets the counter 7 but at such a time, the data of the counter 7 are set while being advanced by one count rather than the prescribed initial value.
Inventors:
Mitsumitsu Nishimura
Application Number:
JP22627593A
Publication Date:
October 28, 2002
Filing Date:
September 13, 1993
Export Citation:
Assignee:
NC Microsystem Co., Ltd.
International Classes:
G06F15/78; H03K21/00; H03K21/38; (IPC1-7): H03K21/00; G06F15/78; H03K21/38
Domestic Patent References:
| JP1269318A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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