To obtain the counter circuit which generates no noise when operating.

Three stages of D flip-flops FF1 to FF3 are connected in series. A delay element 11 outputs a delayed signal S2D by delaying the signal S3 from the Q output of the D flip-flop FF1 by a delay time d2 and a delay element 12 outputs a delayed signal S3D by delaying the signal S3 from the Q output of the D flip-flop FF2 by a delay time d3. Here, the delay times d2 and d3 and a clock cycle Tc are so related that Tc>d2>d3. A 3-input NOR gate G1 receives the delayed signals S2D, S3D, and S4 (Q output of D flip-flop FF3), NORs those signals S2D, S3D, and S4, and outputs a signal S1 to the D input of the D flip-flop FF1.