PURPOSE: To obtain a circuit which detects the fault of a counter without duplexing the counter.

CONSTITUTION: The counted value 2 is outputted from a 4-bit counter 1 and then inputted to a horizontal parity generating circuit 3. The circuit 3 generates the horizontal parity value based on the value 2. Then horizontal parity value is outputted from the circuit 3 and inputted to a fault detecting circuit 4. Then the circuit 4 turns two continuous horizontal parity values into a pair and secures the exclusive OR of both values to generate the checked value. The fault of the counter 1 is decided when the checked value is equal to '0', and a fault detection signal 6 is transmitted from the circuit 4. In regard of the checking timing, a detection timing control circuit 5 instructs a check every two counting operations of the counter 1.