PURPOSE: To reduce number of test pins in the case of testing plural counters by discriminating the coincidence of all common bit outputs of the plural counters and configuring discrimination of even/odd number of 1s in a most frequent bit output in the plural counters.

CONSTITUTION: The device is provided with a selector 107 selecting an input clock for plural counters 108-111 or a test clock, a circuit 116 discriminating the coincidence of all common bit outputs of the counters 108-111, and a circuit 118 discriminating the odd/even parity of number of 1s in an output of the most frequent bit counter 11 among the counters 108-111. Through the constitution above, the coincidence of all common bit outputs of the counters 108-111 is discriminated by an output 117 of the test pin and the even odd parity of number of 1s in the output of the most frequent bits in the counters 108-111 is discriminated by an output 119 of the test pin. Thus, the outputs 17, 119 of the two points are detected to detect whether or not the counters 108-111 are in normal operation.