To prevent erroneous latch of a count value read by a host control part.

When (start timing of) a host control part latch signal 15 from the host control part 23 matches to sampling timing of a sampling clock 18, a reading register latch signal 16 is output from an arbitration circuit 14 at a falling point of the sampling clock 18 at the end point of state change (start) of external pulse input 17, thus, sampling is performed at the center of a low period of the sampling clock 18 at a position where the state change (start) of the external pulse input 17 is terminated and sampling in the middle of the state change of the external pulse input 17 is avoided.