Title:
COUNTER
Document Type and Number:
Japanese Patent JP2998704
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To shorten as test time and to make a test circuit simple by providing a higher-order bit counter, which uses the output of a selecting means as a count signal and a low-order bit counter which has more bits than the higher- order bit counter.
SOLUTION: A 7-bit counter is configured divided into a 4-bit counter 100 and a 3-bit counter 200. Further, an AND gate 300 and a selector 400 are provided. The count signal is inputted to one input terminal of the 4-bit counter 100 and one input terminal of the AND gate 300. The output of the 4-bit counter 100 is inputted to one input terminal of the selector 400 and the other input terminal of the AND gate 300, whose output is inputted to the other input terminal of the selector 400. The selector 400 switches and outputs the outputs of the 4-bit counter 10 and the output of the AND gate 300 with a mode signal. The output signal of the selector 40 is inputted to the 3-bit counter 200.
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Inventors:
Kazunori Nagasaki
Application Number:
JP17325597A
Publication Date:
January 11, 2000
Filing Date:
June 13, 1997
Export Citation:
Assignee:
NEC
International Classes:
G06F11/22; H03K21/40; (IPC1-7): H03K21/40
Domestic Patent References:
| JP258423A | ||||
| JP269022A | ||||
| JP225110A |
Attorney, Agent or Firm:
Asamichi Kato