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Title:
CPU BUS DATA DIAGNOSTIC DEVICE
Document Type and Number:
Japanese Patent JPH03186937
Kind Code:
A
Abstract:

PURPOSE: To detect the error of data fetched in CPU by inspecting the same data as that which CPU fetches.

CONSTITUTION: The output of a CRC calculation part 12 and the output of a CRC storage part 14 are inputted to respective inputs of a comparison part 15 with two inputs and are compared. When they do not coincide, the comparison part 15 outputs an error signal 19. The update of a program counter in an instruction processing part 11, which shows the address of a data memory 17 is stopped by the error signal 19. When a subsequent machine cycle starts with such a state, the address of the data memory 17 which is the same as that where the error occurs, is outputted from the program counter. Thus, a retry as against the occurrence of the error is executed and the error of data fetched in CPU is detected.


Inventors:
KUSUNOKI SHIGEO
Application Number:
JP32687789A
Publication Date:
August 14, 1991
Filing Date:
December 15, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/10; G06F13/00; (IPC1-7): G06F11/10; G06F13/00
Attorney, Agent or Firm:
Uchihara Shin



 
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