To provide an art which utilizes crossbar devices in a reconfigurable circuit.
A crossbar device includes input lines of a first set and output lines of a second set. A plurality of pass transistor chains are provided, and the input lines are coupled to the output lines selectively while reducing parasitic capacitive loads. Memory elements and decoder logic are provided, and selective couplings are controlled easily. A supply voltage increased by Vth is fed to the respective memory elements of the crossbar device, and the input voltages of the corresponding input buffers are maintained at Vdd. Thereby, low-power application to a reconfigurable circuit block of multiple crossbar devices can be improved. A control circuit is coupled through control lines to all the output buffers of the interconnected crossbar devices each other, and the output buffers of these crossbar devices are put in the known power-on state. Thereby, the application of the plurality of crossbar devices to the reconfigurable circuit block is improved.
LEPAPE OLIVIER
Takaaki Yasumura
Natsuki Morishita