To provide a Cu wiring formation method capable of obtaining a Cu wiring with high electromigration resistance without causing a void or the like and without a complicated step and an increase in leak current between wirings.
A Cu wiring formation method comprises the steps of: forming a barrier film 204 on the entire surface of a wafer W including a trench 203; forming an Ru film 205 on the barrier film 204; embedding a Cu film 206 into the trench 203 by forming the Cu film 206 on the Ru film 205 by PVD; forming a stacked layer 207 on the Cu film 206; forming a Cu wiring on the trench 203 by polishing the entire surface of the wafer by CMP; forming a metal cap 209 composed of a manganese oxide film on the entire surface of the wafer W; and forming a dielectric cap 213 on the metal cap 209.
GOMI ATSUSHI
SUZUKI KENJI
HATANO TATSUO
TOSHIMA HIROSHI
MIZUSAWA YASUSHI
JP2006148075A | 2006-06-08 | |||
JP2011023456A | 2011-02-03 | |||
JP2011249794A | 2011-12-08 | |||
JP2009105289A | 2009-05-14 | |||
JP2008147467A | 2008-06-26 | |||
JP2012009788A | 2012-01-12 | |||
JP2007103546A | 2007-04-19 | |||
JP2010021447A | 2010-01-28 | |||
JP2012074522A | 2012-04-12 |
Next Patent: SEMICONDUCTOR DEVICE MANUFACTURING METHOD