To provide a D flip-flop in which data are sent/received at a high speed between integrated circuits (DFFs), a clock skew caused in this case is reduced, and a latch error caused by the skew is prevented.

The DFF 1 is provided with a clock delay circuit 2 in which data are outputted from a data output terminal Q with a clock received by a clock input terminal C and a clock via a transfer gate, a transfer gate equivalent to two buffers is outputted to a clock outptut terminal CO to generate a clock signal whose delay time matches a data delay time Td and the clock is outputted to the clock output terminal CO. Since data and a clock signal are delivered on wiring of the same path to an output connection destination DFF, the effect by the wiring is cancelled and then no problem is caused to high speed transmission of signals between integrated circuits (DFFs).