Title:
DC offset cancellation circuit for a receiver
Document Type and Number:
Japanese Patent JP6219222
Kind Code:
B2
Abstract:
Techniques for cancelling DC offset are described. A DC offset cancellation circuit in a receiver cancels DC offsets caused by leaked LO (local oscillator) signals from a LO signal generator. The receiver first calibrates itself by using the DC offset cancellation circuit during a transmit mode. During the calibration, the DC offset cancellation circuit stores the DC offset voltage signal caused by the leaked LO signals. During a receiving mode when the receiver is receiving a signal, the receiver subtracts the stored DC offset voltage signal from the received signal to cancel the DC offsets caused by leaked LO signals.
Inventors:
Ranhua Sun
Christian Hollenstein
James Jaffee
Christian Hollenstein
James Jaffee
Application Number:
JP2014085623A
Publication Date:
October 25, 2017
Filing Date:
April 17, 2014
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H03F3/34; H04B1/30
Domestic Patent References:
| JP6268552A | ||||
| JP2000286683A | ||||
| JP2001135038A | ||||
| JP10512133A |
Foreign References:
| US20040081256 |
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada
Yoshihiro Fukuhara
Morisezo Iseki
Takashi Okada