Title:
DCDC converter
Document Type and Number:
Japanese Patent JP6343507
Kind Code:
B2
Abstract:
To provide a DCDC converter achieving low power consumption. A clock generation circuit, an error amplifier, a comparator, and a timer are included in a control circuit. The clock generation circuit, the error amplifier, and the comparator each include a bias circuit and a potential hold portion for intermittently holding a constant potential generated in the bias circuit. The potential hold portion includes a capacitor and a switch. The on or off of the switch is intermittently controlled using the timer. Even in a period in which the supply of voltage is stopped, a signal based on a constant potential generated in the bias circuit is continuously output.
Inventors:
Kei Takahashi
Application Number:
JP2014150301A
Publication Date:
June 13, 2018
Filing Date:
July 24, 2014
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H02M3/00
Domestic Patent References:
| JP2010142111A | ||||
| JP6242847A | ||||
| JP201219682A | ||||
| JP2012100522A |
Foreign References:
| US5705891 |