PURPOSE: To decrease the number of transistors (TR) by charging capacitors with weighted voltages as digital signals and by obtaining an output by connecting those capacitors in series.
CONSTITUTION: A reference voltage is applied between terminals 2a and 2b and voltages are developed at connection points 51a, 51b and 51c in 4:2:1 proportion. Digital signals applied to terminals 3L, 3M and 3L control TRs 52, 54, 56, 53, 55, and 57 and voltages corresponding to "1"s of the digital signals are developed at points (g), (h) and (i). An H-level and an L-level voltage are applied to terminals 59a and 59b, respectively, and TRs60, 61 and 62 turn on to charge capacitors 65, 66 and 67 with voltages at points (g), (h) and (i). When the levels of terminals 59a and 59b are both inverted, the capacitors 65, 66 and 67 are connected in series to output an analog voltage, which corresponds to the digital signal, between terminals 71a and 71b.
WO/1999/027653 | DIGITAL TO ANALOGUE CONVERTER AND METHOD OF OPERATING THE SAME |
WO/2022/196118 | IMAGE SENSOR |
JPH02159125 | CONVERTER CIRCUIT |