PURPOSE: To sharply reduce the number of resistances and switches constituting a converting section, by impressing a 1st control signal corresponding to the high-order bits of input digital signals upon the converting section across which a 1st reference voltage is applied.

CONSTITUTION: Assuming that the input digital signal impressed upon an input terminal 8 is f-bit one, the higher-order two bits and lower-order two bits are caused to be respectively selected at selection circuits 9 and 10. Then the output signals of the circuits 9 and 10 are respectively latched by latch circuits 11 and 12 and decoded by decoders(DC) 13 and 14. When switches 15, 27, and 28 are set to the states shown in the figure, the output signal of the DC 13 is impressed upon a converting section 16 and a reference voltage +Vr is applied across the converting section 16. As a result, analog signals of Vr/2 corresponding to the high-order 2-bit signals are generated and held by a holding circuit 29. When the switches 15, 27, and 28 are switched to the opposite states thereafter, analog signals of Vr/16 are held by a holding circuit 30 similarly to the above-mentioned case. The signals held by the circuits 29 and 30 are added to each other at an adder circuit 31.