PURPOSE: To execute a proper error processing by detecting that the direct memory access interval reaches a prescribed time or over so as to detect the defect of the direct memory access control.

CONSTITUTION: A communication control section 4 receives a transmission packet in terms of DMA from a RAM 3 via a DMAC 5 and sends the packet to a destination device designated via a control memory sequentially. Whether or not all the transmission packets are finished for transmission is checked and when the transmission processing is not finished, whether or not timeout of an end watching timer 6 is detected is checked, and in case of timeout, it is discriminated to be an improper operation of the DMAC 5 to apply error recovery processing. Thus, proper recovery processing is attained.