PURPOSE: To obtain a high speed data communication coping with an error of a PLL circuit by using a parity error detection circuit to output an error detection signal.

CONSTITUTION: A parity error detection circuit 68 is provided, which uses an addition taking 3 as a modulus while inputting a time interval data with parity so as to check whether or not a received data is correct. Then an output of an MFM modulator is grasped as a time interval data, a parity code addition circuit adds a redundancy code as the time interval data, sends the result to a communication line, a receiver recovers the similar time interval data to that above based on a window signal generated by the PLL circuit to check the presence of an error by a parity error detection circuit 68. Thus, even with the presence of a frequency variance of the window signal due to the error in the PLL circuit, the error in the received data is not expanded after the time of error in the PLL circuit and the error of the receiving data is suppressed to a time interval only of a pulse train at the erroneous time.