PURPOSE: To reduce the scale of IC and to obtain a data converter of low cost by creating a data converter that does not require a multiplexer.

CONSTITUTION: When a series parallel conversion number (split phase number) is N (integer), a deserializer 20 is constituted of N first latch circuits 21∼28 and serial data are latched successively based on latch pulses CK1∼CK8 made by dividing serial data clock CK0 to 1/N. Latched parallel data of N-divided phase are latched by eight second latch circuit groups 40 simultaneously, and parallel data of the same divided phase outputted by the second latch circuit groups 40 are supplied to corresponding I/O ports 13A∼13D. In this constitution, the initial phase (the first phase) of the first latch circuit 21 of the first latch circuits 21∼28 are latched. Accordingly, even when series parallel conversion number changes, a latch circuit that latches data of the first phase is not necessary. Therefore, parallel data of the first phase are always supplied to I/O port corresponding to the phase, and conventional multiplexer becomes unnecessary.