PURPOSE: To improve the system processing speed by reading address information stored in advance after a serial data comprising bit parallel words and using this information to read serially one by one bit of data.

CONSTITUTION: A selection circuit 4 selects a word address WWA from an adaptor 10 by the number of times of serial words' share of a serial data comprising bit parallel words, applies the result to a data storage circuit 1 and stores the bit parallel data PD to a word location designated by the WWA from the adaptor 10 at every occasion. The address information to designate the output bit order of the bit serial data is stored in advance in the address storage circuit 2. The circuit 4 acts like selecting the word address RWA outputted from the circuit 2 and applying it to the circuit 1. The bit parallel data designated by the RWA is read to the selection circuit 5 from the data storage circuit 1.