Title:
DATA DECODING CIRCUIT, VOLTAGE CONTROLLED OSCILLATION CIRCUIT, DATA DECODER AND ELECTRONIC APPLIANCE
Document Type and Number:
Japanese Patent JP3508412
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To accurately decode received split-phase codes and Manchester codes, etc., without requesting high performance to a reception circuit by providing a means for sampling reception data reproducing signals based on bit synchronizing signals and the means for converting sampled signals to serial binary data.
SOLUTION: An edge detection part 1 is composed of a differentiation circuit for inputting reception data 101 and detecting a change point, detects the rise of the reception data 101 and generates edge detection output signals 102. A pulse generation part 3 outputs the reception data reproducing signals 104 and timing signals 103 for phase comparison with the rise of the edge detection output signals 102 as a trigger. A sampling part 5 outputs the signals obtained by performing frequency division from synchronizing signals 105 generated by a phase synchronization generation part 4 as the bit synchronizing signals 106, samples the reception data reproducing signals 104 and outputs the serial binary data 107.
Inventors:
Ishida, Takuya
Aoki, Kanji
Aoki, Kanji
Application Number:
JP22048696A
Publication Date:
March 22, 2004
Filing Date:
August 02, 1996
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
H03K3/354; H03B5/26; H03M5/12; H04L7/027; H04L7/033; H04L25/48; H04L25/49; (IPC1-7): H04L25/49; H03M5/12
Attorney, Agent or Firm:
井上 一 （外２名）
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