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Title:
DATA DEMULTIPLEX AND MULTIPLEX SYSTEM AT PLURAL CHANNEL TRANSMISSION
Document Type and Number:
Japanese Patent JPH0398343
Kind Code:
A
Abstract:

PURPOSE: To easily match the phase by providing plural demultiplex multiplex means, plural 1st clock transfer means and plural end clock transfer means.

CONSTITUTION: A 1st clock transfer means 121 inputs a received data synchronously with a common clock signal to a demultiplex/multiplex means 111 and an output of each demultiplex/multiplex means 111 is sent to each channel with the 2nd clock transfer means 131 synchronously with the transmission clock signal of each channel to attain the operation of each demultiplex/ multiplex means 111 synchronously with the common clock signal. when the demultiplex/multiplex means 111 is operated synchronously with the common clock, since the phases of data of plural channels are made coincident, it is not required to match the phase for each occasion as to the data after demultiplexing or before multiplexing. Thus, the data phase matching via plural channels is facilitated.


Inventors:
KOMORI HISAFUMI
SHIWACHI SHINICHI
Application Number:
JP23544389A
Publication Date:
April 23, 1991
Filing Date:
September 11, 1989
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L25/38; H04L7/00; H04L25/40; H04L29/06; H04Q3/60; (IPC1-7): H04L7/00; H04L25/38; H04L25/40; H04L29/06; H04Q3/60
Attorney, Agent or Firm:
Furuya Fumio