Title:
DATA ERASING METHOD AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JPH1139892
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a data erasing method having realized high reliability without complicating a circuit structure and a device structure and also provide a non-volatile semiconductor storage device using the same method. SOLUTION: This non-volatile semiconductor storage device is formed of a memory cell 1, an erasing circuit 2 and a resistance element 3. In this non- volatile semiconductor memory device, a control gate 11 is grounded and a high voltage generated from an erasing circuit 2 is impressed to the source 12 via a resistance element 3. Upon impression of high voltage, an easing current flows to a memory cell 1. This current includes an extra current because tunneling current between bands is also generated. When this current is generated, voltage drop is generated by the resistance element 3 and thereby the voltage to be impressed to the source 12 of the memory cell 1 is controlled. Here, when the resistance element 3 is formed of a transistor, a voltage which flows only the current required for erasing can be obtained by optimizing the size of such resistance element.
Inventors:
KOMIYA MANABU
Application Number:
JP18834797A
Publication Date:
February 12, 1999
Filing Date:
July 14, 1997
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G11C16/02; G11C16/06; (IPC1-7): G11C16/06; G11C16/02
Attorney, Agent or Firm:
Miyai Akio