PURPOSE: To ensure the set map time of a data by branching the 2nd data path from this side of a delay means in the 1st data path and relaxing the effect of delay means to the 2nd bit data to be transferred via the 2nd data path.

CONSTITUTION: A delay circuit 2 and the 1st clocked inverter circuit 3 fetching the data fed from the delay circuit 2 based on the 1st timing signal 1 are arranged to the 2nd data path DP1 after the branch point of both data paths DP1, DP2. The 1st timing signal 1 controlling the data fetch by the 1st clocked inverter circuit 3is formed by a timing generator 1 based on a system clock signal 0. Thus, the timing signal 1 is delay slightly to the system clock signal 0. Then at the time of fetching a data via the 1st clocked inverter circuit 3 for data fetch, the delay circuit 2 is provided at this side of the clocked inverter circuit 3 in order to prevent deterioration of a data hold time.