PURPOSE: To correct the advancement of a frequency divider automatically by resetting each frequency divider of plural data multiplexing circuits when the duty ratio of an output of a gate circuit is deviated in a prescribed direction with respect to a prescribed ratio.

CONSTITUTION: An output D3 of a frequency divider 11 and an output D4 of a frequency divider 21 are pulse signals of opposite phase whose duty ratio is 50% after a point of time tx causing an error, and the duty ratio of an output GO of a gate circuit 60 reaches 100%. Then an output voltage Vi of an integration circuit 71 is gradually increasing toward -0.8V and an output CP of a comparator 72 goes to a high level at a pint of time ty when the voltage Vi is higher than -0.1V, a reset signal is caused in the output CP and the reset signal is fed to frequency dividers 11, 21, 31 through an OR gate 73 to reset the frequency dividers 11, 21, 31. Thus, the advancement of the frequency dividers 11,21 is arranged after the point of time ty and the sequence of multiplexing of input pattern data 11-14 in the output pattern data O3 is the initial sequence.