Title:
DATA OUTPUT BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JP3113853
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To decrease noises to be produced when applying a minus potential to an input/output pad by generating a noise suppress signal by detecting the level of signal impressed to the input/output pad, and suppressing the bias increase of substrate caused by a potential difference between the gate and source of pull-up transistor based on the noise suppress signal.
SOLUTION: When impressing low-level data to an input/output pad 20, the output of data input buffer 26 is turned into low level so that a WEB signal keeps a low level during writing operation, and the output value of 1st NOR gate 28 becomes a high-level VCC. The high-level output of 1st NOR gate 28 is impressed to the gate electrode of clamp transistor 23, a pull-up transistor 21 is completely turned on, and the potential difference between the gate and source of pull-up transistor 21 is turned to '0'. Thus, the noises caused by the potential difference of gate/source can be suppressed.
Inventors:
Dong Kyun Kim
Application Number:
JP1018198A
Publication Date:
December 04, 2000
Filing Date:
January 22, 1998
Export Citation:
Assignee:
ELGE SEMICON Company Limited
International Classes:
H03K17/16; G11C11/407; H03K17/693; H03K19/003; H03K19/0175; (IPC1-7): H03K17/16; H03K17/693; H03K19/0175
Domestic Patent References:
| JP59208942A |
Attorney, Agent or Firm:
Hironobu Onda