Title:
DATA OUTPUT CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3030621
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enhance the processing speed of a semiconductor memory and to reduce power consumption of the memory by generating the output of a zero level from an output driving while directly controlling the output of a data output buffer by using an address transition detection signal in an address transition.
SOLUTION: The high level output of an address transition detection signal ATD is supplied to a data output buffer 13 as a selection signal SEL by being delayed by a prescribed time with a delay unit 4 and also the signal is directly supplied to it as a kill signal KILL. When an address is made to transit, the address transition detection signal ATD becomes a low level for a prescribed time, that is, the kill signal KILL becomes the low level and the data output buffer 13 controls so that the output DQ of an output driving part 13A becomes a zero level for the period of the low level of the signal KILL. Thus, erroneous data are prevented from being outputted from the driving part 13 and the processing speed of a semiconductor memory is enhanced and power consumption of the memory is reduced.
Inventors:
Ifan Park
Hyunsoo Shin
Hyunsoo Shin
Application Number:
JP20047697A
Publication Date:
April 10, 2000
Filing Date:
July 25, 1997
Export Citation:
Assignee:
ELGE SEMICON Company Limited
International Classes:
G11C11/41; G11C7/10; G11C11/407; G11C11/409; G11C11/413; (IPC1-7): G11C11/413; G11C11/401; G11C11/409; G11C11/41
Domestic Patent References:
| JP684364A |
Attorney, Agent or Firm:
Fumio Sasashima (1 person outside)