Title:
データ再生回路
Document Type and Number:
Japanese Patent JP4668750
Kind Code:
B2
Abstract:
A data reproduction circuit for receiving data and reproducing the data and its clock which comprises a clock generation circuit (182) for generating a clock for over-sampling the data, an over-sampling determination circuit (181) for sampling the received data by a clock with frequency higher than the data rate of the received data and converting the sampled data into digital signals, a data selection circuit (183) for selecting and outputting the reproduced data by determining the digital signals based on a first reproduced clock and a circuit for generating a signal for controlling a second reproduced clock for generating the first reproduced clock, a clock selection circuit (184) for selecting the second reproduced clock and a phase-locked loop (PLL) circuit for reducing the jitters of the second reproduced clock and generating the first reproduced clock.
More Like This:
Inventors:
Yasutaka Tamura
Application Number:
JP2005271024A
Publication Date:
April 13, 2011
Filing Date:
September 16, 2005
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04L7/033; H03H17/00; H04L25/08
Domestic Patent References:
| JP2002190724A | ||||
| JP5167570A | ||||
| JP2003204262A | ||||
| JP2002025202A | ||||
| JP2003333021A | ||||
| JP2004537909A |
Attorney, Agent or Firm:
Yoshiyuki Osuga
Motoaki Hisagi
Motoaki Hisagi