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Title:
DATA POSITION DETECTION CIRCUIT IN FRAME FORMAT OF DIGITAL TRANSMISSION SYSTEM
Document Type and Number:
Japanese Patent JPH0537590
Kind Code:
A
Abstract:

PURPOSE: To decrease number of gates and to simplify the circuit scale by comparing a pointer of a pointer latch section with a count of a frame counter section and outputting a signal representing the presence of a specific data of a channel.

CONSTITUTION: A detection section 1 latches overhead bytes H1, H2 of each channel from an inputted STS-n serial data. Then 10-bits are extracted as a pointer PV from the bytes H1, H2 and latched to a pointer latch section 2. A frame counter section 5 counts a clock CK from an internal timing generating section 4 and outputs the count CV to the byte in the frame to a comparator section 6. The comparator section 6 compares the count CV with the pointer PV from the latch section 2 and outputs a signal representing a specific data J1 when they are coincident. Thus, one counter is enough for the purpose irrespeclwely of the number of channels of signals and the circuit is simplified.


Inventors:
IMAI EIJI
Application Number:
JP18222991A
Publication Date:
February 12, 1993
Filing Date:
July 23, 1991
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04J3/00; H04L7/08; H04L29/08; (IPC1-7): H04J3/00; H04L7/08; H04L29/08
Attorney, Agent or Firm:
Teiichi