Title:
DATA PREFETCH METHOD FOR MULTIPLE LOOP, PROCESSOR AND PROGRAM GENERATING METHOD
Document Type and Number:
Japanese Patent JP3546341
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To shorten an inner-most loop length and to convert a program so as to effectively perform prefetch even to a multiple loop having the long loop length of outside loop.
SOLUTION: The selection of prefetch object loop is performed for the inner- most loop of multiple loop (502). Index cluster division is applied to the selected loop and it is divided into the first half partial loop and the latter half partial loop (504). The prefetch instruction of data to be used for the relevant loop itself is inserted into the first half partial loop, and the prefetch instruction of data to be used for the next prefetch object loop is inserted into the latter half partial loop (505). Thus, the time of wait due to main memory reference can be sufficiently reduced and the execution of computer program can be accelerated.
Inventors:
Hiroyasu Nishiyama
Application Number:
JP10042997A
Publication Date:
July 28, 2004
Filing Date:
April 17, 1997
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F9/30; G06F9/32; G06F9/38; G06F9/45; G06F12/08; (IPC1-7): G06F9/45; G06F12/08
Domestic Patent References:
| JP10283192A |
Other References:
位守弘充・他,「擬似ベクトル処理向きメモリアーキテクチャの一提案」,情報処理学会研究報告,日本,社団法人情報処理学会,1991年11月22日,Vol.91, No.100(91-ARC-91),pp.61-68
Mowry, T.C.,et.al.,"Design and Evaluation of a Compiler Algorithm for Prefetching",ACM SIGPLAN NOTICES,1992年 9月,Vol.27, No.9,pp.62-73,JST資料番号:D0915A
Mowry, T.C.,et.al.,"Design and Evaluation of a Compiler Algorithm for Prefetching",ACM SIGPLAN NOTICES,1992年 9月,Vol.27, No.9,pp.62-73,JST資料番号:D0915A
Attorney, Agent or Firm:
Ari Chika Genshiro