Title:
DATA PREPARATION METHOD FOR LOGIC SIMULATION, LOGIC SIMULATION METHOD AND LOGIC SIMULATOR
Document Type and Number:
Japanese Patent JP2948437
Kind Code:
B2
Abstract:
PURPOSE: To perform accurate logic simulation by expressing the relation characteristics of an element for logic simulation to operation verification components by plural characteristic graphs without expressing them by one polygon line graph and preparing data for the logic simulation based on the characteristic graphs.
CONSTITUTION: This simulator is provided with a storage means 14 for storing the data DLS for the logic simulation for verifying the operation of a semiconductor integrated circuit 13, an operation verifying means 15 for verifying the operation of the semiconductor integrated circuit 13 based on the data DLS for the logical simulation and a control means 16 for controlling the input/output of the operation verifying means 15 and the storage means 14. The data DLS for the logic simulation are stored in the storage means 14 and the data DLS for the logic simulation are provided with a data structure for which the relation characteristics of the element CL for the logic simulation to the operation verification component T of a logic cell 11 obtained based on a circuit simulation processing.
Inventors:
YOSHIKAWA SATOSHI
TANIZAWA SATORU
TANIZAWA SATORU
Application Number:
JP5906993A
Publication Date:
September 13, 1999
Filing Date:
March 18, 1993
Export Citation:
Assignee:
FUJITSU KK
International Classes:
G06G7/48; G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP4237143A | ||||
| JP1271869A | ||||
| JP61265622A |
Other References:
豊田徹、外３名、”ＶＬＳＩ遅延ライブラリ作成支援システム”、情報処理学会研究報告（９８−ＤＡ−５８−９）、情報処理学会、１９９１年、Ｖｏｌ．９１、Ｎｏ．５８、ｐ．９．１〜９．８
Attorney, Agent or Firm:
Keizo Okamoto
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