Title:
デバイスにおけるデータ処理エンジン構成
Document Type and Number:
Japanese Patent JP7398384
Kind Code:
B2
Abstract:
A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.
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Inventors:
No Game No Life, Juan Jota
Bilsky, Golan H.K.
Langer, Jean
Ozgul, Barsh
Tim, Touan
Barque, Richard El
Bittig, Ralph Day
Cornellis Ah, Fissels
Dick, Christopher H
Clark, David
James-Roxby, Philip Bee
Bilsky, Golan H.K.
Langer, Jean
Ozgul, Barsh
Tim, Touan
Barque, Richard El
Bittig, Ralph Day
Cornellis Ah, Fissels
Dick, Christopher H
Clark, David
James-Roxby, Philip Bee
Application Number:
JP2020554278A
Publication Date:
December 14, 2023
Filing Date:
April 02, 2019
Export Citation:
Assignee:
XILINX INCORPORATED
International Classes:
G06F15/173; G06F9/38; G06F12/00; G06F13/16; G06F15/78; G06F15/80
Domestic Patent References:
| JP64500306A | ||||
| JP2001312481A | ||||
| JP2017199371A | ||||
| JP2008250846A | ||||
| JP2003534596A | ||||
| JP1263858A |
Foreign References:
| US9652410 | ||||
| US20180012637 |
Attorney, Agent or Firm:
Patent Attorney Fukami Patent Office