Title:
DATA PROCESSING SYSTEM CONTAINING ENCODER, DECODER AND WRITING PRECOMPENSATION CIRCUIT
Document Type and Number:
Japanese Patent JPS61296577
Kind Code:
A
Abstract:
A data processing system employs a run-length limited code and incorporates an encoder and decoder sharing common circuits, including a data shift register, a code shift register and a write precompensation logic circuit. Data bits are processed as single words or double words depending upon the pattern of data bits as they are shifted.
Inventors:
ROBAATO ERU KUROOKU
Application Number:
JP14800286A
Publication Date:
December 27, 1986
Filing Date:
June 24, 1986
Export Citation:
Assignee:
PRIAM CORP
International Classes:
G11B5/09; G11B20/10; G11B20/14; H03M5/14; H03M9/00; (IPC1-7): G11B5/09; G11B20/14; H03M9/00
Attorney, Agent or Firm:
Minoru Nakamura
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