To adjust the timing of data input and to execute a high speed arithmetic processing by providing a direct path for feeding back an arithmetic processing result.

Data a70 being common to a final row in a lateral direction and a first column in a vertical direction are not read after they are stored in a one block buffer 5 but they are directly transferred from a serial-parallel conversion register 3 at the time of shift from one dimension to two dimension by shift from the lateral direction to the vertical direction. Thus, the processing can be executed while the processing timing of look-ahead on next data is held and a clock can be reduced.