Title:
DATA PROCESSOR
Document Type and Number:
Japanese Patent JPH05120154
Kind Code:
A
Abstract:
PURPOSE: To improve the reliability of a data processor where the control, information are stored in plural electrical erasion/rewrite enable ROMs (EEPROMs) by preventing the concentration of rewrite to a specific EEPROM.
CONSTITUTION: A decoding circuit 17 decodes the (n) bits of lower order of an address bus 12 with use of the EEPROM 131 and 132. The chip enable terminals CE of both EEPROM 131 and 132, are exclusively controlled based on the decoding result of the circuit 17. So that the EEPROM to receive an access is selected. Then the address input terminals A0-An-1 of the EEPROM 131 and 132 are connected to the remaining address lines excluding the (n) bits of lower order of the bus 12.
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Inventors:
UGAWA SHINJI
Application Number:
JP28451191A
Publication Date:
May 18, 1993
Filing Date:
October 30, 1991
Export Citation:
Assignee:
SHIKOKU NIPPON DENKI SOFTWARE
International Classes:
G06F12/16; G11C16/02; G11C16/06; G11C17/00; (IPC1-7): G06F12/16; G11C16/06
Attorney, Agent or Firm:
Wakabayashi Tadashi