Login| Sign Up| Help| Contact|

Patent Searching and Data

Document Type and Number:
Japanese Patent JPS6140658
Kind Code:

PURPOSE: To connect a high-speed I/O, which can access directly a memory, to even a relatively low-speed common bus with a bus constitution by transferring data in a high speed through an input/output signal connected directly to the memory control.

CONSTITUTION: A memory access request passing a common bus 10 or that from a high-speed I/O 13 is selected by the timing determined by a memory control circuit 23. That is, outputs of a low-speed I/O 12 and the high-speed I/O 13 are stored in registers 24 and 25 respectively at a timing C, and a switching selecttion signal SEL goes to "1" to select the memory access request from the high- speed I/O 13. At the next timing, the read cycle is executed by the memory access request from the high-speed I/O13. If the signal SEL is set to "0" simultaneously, the memory access request from the bus 10 is selected. Thus, the high- speed I/O which can access directly a main memory 16 is connected to the bus 10 with the bus constitution.

Application Number:
Publication Date:
February 26, 1986
Filing Date:
July 31, 1984
Export Citation:
Click for automatic bibliography generation   Help
International Classes:
G06F13/36; G06F13/16; G06F13/28; (IPC1-7): G06F13/20
Attorney, Agent or Firm:
Toshi Inoguchi

Previous Patent: Bed apparatus

Next Patent: JPS6140659