Title:
DATA PROCESSOR
Document Type and Number:
Japanese Patent JPS62113259
Kind Code:
A
Abstract:
PURPOSE:To eliminate malfunction in I/O processing by supplying a switching signal to plural processors and then supplying a delay switching signal which connects one processor to an input/output interface after a delay period set longer than a period in which I/O processing operation is stopped. CONSTITUTION:Plural processors MPA and MPB, the input/output interface IF, an I/O bus B which connects the input/output interface to the plural processors, and the changeover switch SW which is interposed in the I/O bus and connects one of the plural processors MPA and MPB to the I/O bus are provided. Further, a switching signal generating means is provided to supply switching signal generating means is provided to supply switching signals SA and SB which allow one processor selected according to a switching command to start I/O processing operation and inhibits the other processor from performing I/O processing operation to the plural processors and also supplies the delay switching signal SC for connecting one processor to the input/output interface to the changeover switch SW after the delay time longer than the stop period of the I/O processing operation of the processor in the I/O processing operation.
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Inventors:
ASAHARA TOYOHIRO
TANAKA TOSHIFUMI
TANAKA TOSHIFUMI
Application Number:
JP25353685A
Publication Date:
May 25, 1987
Filing Date:
November 12, 1985
Export Citation:
Assignee:
NISSIN ELECTRIC CO LTD
International Classes:
G06F15/16; G06F15/17; G06F15/177; (IPC1-7): G06F15/16
Attorney, Agent or Firm:
Miyai Akio