PURPOSE: To obtain a receiver having a simple constitution that can obtain a receiving completion signal, to eliminate the necessity of a conventional clock counter and to reduce the chip area of an integrated circuit by adding the register of 1 bit to a receiving register, and initial setting in the register at the starting time of receiving.

CONSTITUTION: An additional register 3 by 1 bit that changes an output signal simultaneously with the completion of receiving is connected to an original receiving register 1. The additional register 3 receives data which are shifted in the receiving register 1 synchronously with receiving clock T, and received data themselves are outputted as its output, and this is made a receiving completion signal C. A receiving start signal P is inputted to the receiving register 1 and additional register 3, and the contents of the two registers are initially set just before starting of receiving.