To provide a redundancy multiplexer circuit technique with improved integrated circuit area efficiency, in which complexity of a circuit, die area necessary to support a complementary control signal in a memory device IC and redundant elements, and undesired parasitic capacitance are reduced.

Redundancy multiplexer circuit technique with an improved integrated circuit area efficiency provides similar functionality to conventional CMOS transmission, or 'pass' gates while concomitantly reducing circuit complexity, the die area necessary to support the redundant elements and the complementary control signals in the memory devices ICs and undesired parasitic capacitance. This technique is achieved by utilizing the on-chip boosted voltage level (Vpp) to supply the voltage for the control signal applied to a single N- channel transistor pass gate. Higher throughput speeds in the address and data paths can be obtained by the significant reduction in undesired parasitic capacitance.