Title:
演算およびスリープ・モード中のデータ格納回路並びに方法
Document Type and Number:
Japanese Patent JP5232638
Kind Code:
B2
Abstract:
The application relates to a circuit for storing a signal during sleep mode, said embodiments of the circuit comprising: a sleep signal input operable to receive a sleep signal; a clock signal input operable to receive a clock signal; a plurality of latches clocked by said clock signal, at least one tristateable device clocked by said clock signal, said at least one tristateable device being arranged at an input of at least one of said plurality of latches, said at least one tristateable device being operable to selectively isolate said input of said at least one latch in response to a predetermined clock signal value; clock signal distribution means operable to distribute said clock signal to said plurality of latches and said at least one tristateable device; wherein in response to a sleep signal said circuit is operable to: reduce a voltage difference across at least a portion of said circuit such that said portion of said circuit is powered down; and maintain a voltage difference across at least one storage latch, said at least one storage latch being said at least one of said plurality of latches; said clock signal distribution means being operable to hold said clock signal at said predetermined value such that said input of said storage latch is isolated.
Inventors:
Frederick, Merlin, Jr.
Kinkade, Martin, Jay
Kinkade, Martin, Jay
Application Number:
JP2008502460A
Publication Date:
July 10, 2013
Filing Date:
March 17, 2006
Export Citation:
Assignee:
RM Limited
International Classes:
H03K3/037; H01L21/822; H01L27/04
Domestic Patent References:
| JP11112297A | ||||
| JP2002198793A | ||||
| JP11355106A | ||||
| JP11330918A | ||||
| JP2001257566A | ||||
| JP2000244287A | ||||
| JP2001251180A | ||||
| JP60224319A | ||||
| JP5206792A | ||||
| JP8195650A | ||||
| JP11289246A | ||||
| JP11214962A | ||||
| JP9261013A | ||||
| JP200226711A |
Foreign References:
| WO2003100830A1 |
Other References:
「0.5μm低電圧フルカスタムLSI設計技術」 松谷・武藤他、NTT R&D Vol.43、No.3、1994
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Akira Iwami
Takayuki Hatanaka
Hajime Asamura
Akira Iwami
Takayuki Hatanaka